Many wireless systems implement encoders and decoders for reliable transmission of data across wireless channels. The purpose of forward error correction (FEC) is to improve the capacity of a channel by adding carefully designed redundant information to the data being transmitted through the channel. The process of adding this redundant information is known as channel coding. The two major forms of channel coding are convolutional coding and block coding. Convolutional codes operate on serial data, one or a few bits at a time, while block codes operate on relatively large (e.g., couple hundred bytes) message blocks.
The most popular among the schemes is the use of Binary Convolutional Codes (BCCs) for encoding the data and a Viterbi decoder for decoding the data. Viterbi decoding at the receiver is one of the most sophisticated blocks in the physical layer.
With the FCC recently (2002) providing GHz bandwidth in the unlicensed spectrum, it is now possible to provide data rates exceeding Gigabytes per second (Gbps) in wireless systems. However, providing Gbps data rates in a wireless system using convolutional encoding and Viterbi decoding requires the processing of more than a billion sequential Add-Compare-Select (ACS) operations in one second. This task is not possible to achieve with current state of the art hardware, as the time needed to perform an ACS operation exceeds one nanosecond. Hence, multiple Viterbi decoders are needed to operate in parallel to meet real-time constraints. Unfortunately, this solution greatly increases hardware complexity and reduces the efficiency of the Viterbi decoder.
This is a relatively new problem, since previously not enough bandwidth was available in wireless systems to make it an issue. Hence, there was no need to design such high speed decoders. Current Viterbi decoders can go up to 480 Mbps for systems using Ultra-Wide Band (UWB). Multiple decoders make Gbps rate possible but at a significant increase in hardware cost.
Therefore, it would be desirable to have a solution for designing Gbps wireless systems with reduced decoder complexity compared to traditional designs for Gbps systems.